EDN

Models for high-voltage transistors in a standard CMOS process

Designers of electronics and communications systems are constantly faced with the challenge of integrating greater functionality on less silicon area. Many of the system blocks – such as power ...
NextBigFuture

Breakthrough Pseudo CMOS Transistors for 1000 Times More Efficient Computing

As transistors are scaled to smaller dimensions, their static power increases. Combining two-dimensional (2D) channel materials with complementary metal–oxide–semiconductor (CMOS) logic architectures ...
Business Wire

ams offers truly scalable transistors in High-Voltage CMOS

UNTERPREMSTAETTEN, Austria--(BUSINESS WIRE)--The Full Service Foundry division of ams AG (SIX:AMS), a leading provider of high performance analog ICs and sensors, today announced a further expansion ...
NextBigFuture

Intel surrounding CMOS with new device architectures using new materials such as magnetic memories, Qubits, GaN transistors

Keynote speaker, IEEE Fellow Kevin Zhang, vice president of Intel’s Technology and Manufacturing Group, also Intel Director of Circuit Technology who led processor development from the 90-to-22 ...
EDN

Post-fabrication process resizes analog transistors

SEATTLE — A startup founded by EDA industry icon Carver Mead has developed a process for recharacterizing CMOS transistors after they've been fabricated. Impinj Inc. is betting the process will be ...